RISC-V open source: from buzzword to escape hatch
RISC-V open source design refers to creating processors, computers, and operating systems around an instruction set and hardware architecture that individual developers can implement, extend, and share without being locked inside a single vendor’s proprietary ecosystem, enabling truly DIY computing systems and custom chip design efforts that are owned by their creators rather than by closed platforms.
The heart of this shift is not a marketing campaign but a set of choices makers are already making. When a hobbyist can build a late‑1980s‑style personal computer on an inexpensive FPGA board and drop in a 25 MHz RISC‑V core instead of a 286 or 386 CPU, that is more than nostalgia. It is a proof of concept that open hardware architecture can stand where proprietary silicon once ruled. The lesson is blunt: if you can define your own CPU in code, you are no longer beholden to a chip catalogue or a licensing department.
This is why RISC‑V matters. It turns CPUs into software‑defined components, and that demolishes old assumptions about who is allowed to build a computer. The question is no longer whether a big vendor supports your idea, but whether you are willing to synthesize it into gates.
GateMate and System/359: one board, many computers
If you want to see how far open hardware architecture has come, look at what one developer squeezed out of a single FPGA board. On a €50 Olimex GateMate A1‑EVB board (about $57), he implemented the GateMate Personal Computer, a machine comparable to a high‑end late‑1980s IBM PC‑compatible that swaps the traditional 286 or 386 for a 25 MHz RISC‑V core. That is not a dev board demo; it is a full homebrew PC, complete with VGA output, 80x30 Hi‑Color text, 8 KB of ROM with a BIOS, and its own OS, GMDOS.
This is custom chip design in practice, not theory. The video controller is an original design, and he bolted on 8 MB of extra PSRAM via a QSPI interface. On the same hardware, he built a miniature mainframe, the System/359, inspired by classic System/360 machines but updated with little‑endian bytes, opcode‑first encoding, PC‑relative addressing, and a modernized channel I/O model. The declaration is explicit: "inspired by, not compatible with".
This dual‑identity board is the real revolution. A single, openly documented platform morphs from PC to mainframe because the architecture is malleable and the instruction set is free to implement. That is what breaking chip lock‑in looks like up close.
Self-hosted Pi stacks show why openness matters to users
Open hardware only matters if it changes everyday computing. The Raspberry Pi shows how DIY computing systems can shift power toward users even before RISC‑V boards flood the market. A single‑board computer can run anything from Python scripts to Docker containers for a homelab, and one writer’s Pi 3B+ now quietly runs three self‑hosted apps without skipping a beat.
Pi‑hole, for example, acts as a network‑wide DNS sinkhole that intercepts every DNS query and blocks those heading to trackers, telemetry endpoints, and ad servers, giving every device on the network the benefit instead of only one browser. Vaultwarden stores passwords locally so there is no subscription, no cloud dependency, and no sensitive data on someone else’s server. A self‑hosted monitoring tool like Uptime Kuma provides alerts when services fail, using under 100 MB of RAM on the Pi 3B+’s ARM64 Docker image.
These tools show why people will care about RISC‑V open source hardware. When small boards already run ad‑blocking, password managers, and monitoring stacks at home, the next logical step is wanting the CPU and OS themselves to be as open as the apps they host.
From QNX ports to QSOE: operating systems without gatekeepers
Hardware freedom is hollow without operating systems that share the same ethos. Over Christmas 2020, one developer decided the timing was right to attack this problem because, in his words, "RISC‑V had matured" and "the toolchains were stable". He ported the QNX 6.4 kernel to RISC‑V, starting from 32‑bit ILP32 sources that had targeted x86, ARM, MIPS, SH, and PPC but had no 64‑bit or RISC‑V port.
He then went further, turning that experience into a ground‑up reworking of the 32‑bit codebase into a 64‑bit LP64 system for RISC‑V, with deliberate simplifications; he calls the result QRV. By the end of April, QRV v0.27 could boot to multi‑user login, and a month later he declared the project finished with version 0.43, calling it his last development post for QRV.
Instead of waiting for vendors to open their kernels, he applied what he learned from earlier projects and built his own system. The successor, QSOE, ships in two variants that share one userspace and build system, runs either on a custom Skimmer microkernel or on the seL4 kernel, and its version 0.1 is already on GitLab under the Apache 2.0 license. That is what decentralized OS innovation looks like: one person, two kernels, and no permission slips.
Why decentralized hardware innovation is here to stay
Taken together, these stories show a clear direction of travel. Makers are moving from using open‑source software on closed chips to building whole stacks—hardware, firmware, kernel, and apps—that are theirs from top to bottom. A Pi 3B+ running Pi‑hole, Vaultwarden, and Uptime Kuma proves how much control self‑hosted users can claw back without subscriptions or third‑party clouds.
On the hardware side, a €50 FPGA hosting a 25 MHz RISC‑V PC, an original video controller, extra PSRAM, and a miniature System/359 mainframe proves that individual developers can match, and sometimes out‑imagine, established manufacturers. There is even a working assembler with the powerful NASM macroprocessor behind the mainframe project, underscoring how mature the toolchain has become.
The conclusion is unavoidable: RISC‑V open source and open hardware architecture are not niche hobbies; they are the early stages of a decentralised hardware economy. As more boards, OS projects like QRV and QSOE, and DIY computing systems appear under permissive licenses, the old model of proprietary chip lock‑in starts to look less like stability and more like unnecessary restraint.
