From Experimental Cores to Production-Grade Open Silicon
Pavona marks a shift in open source silicon from isolated IP blocks to a full production-grade distribution aimed at real devices. Launched by GlobalPlatform, the project brings together certification-ready security IP, silicon-proven reference designs and what it calls the first openly available post-quantum cryptography stack for embedded silicon. Unlike earlier efforts focused on single cores or static reference chips, Pavona is built as a composable platform. Designers can pick and assemble secure subsystems tailored to their architecture rather than being locked into a monolithic design. Two taped-out roots of trust at TSMC 3nm demonstrate that this IP is not just theoretical, but already exercised in real silicon. Backing from industry and academic players under an independent governance model signals that open source silicon is moving toward a mature ecosystem rather than a collection of one-off experiments.
Security by Design: Roots of Trust for Connected Devices
For IoT security hardware, decisions made in silicon often outlast any software update. Pavona targets this reality by packaging roots of trust, cryptographic acceleration and certification-aligned architectures directly into its open source silicon distribution. It launches with two key reference designs: a standalone chip root of trust and an integrated root of trust for chiplet-based systems, both already taped out. These designs are intended as blueprints for secure hardware design across use cases, from constrained IoT nodes to high-performance systems. Aligning with frameworks such as FIPS 140-3 and Common Criteria, Pavona does not automatically certify products, but it gives designers an architecture built with certification workflows in mind. That means OEMs can start from a root of trust explicitly designed to anchor device identity, secure boot and key protection, instead of bolting security on later at the board or firmware level.
Post-Quantum Cryptography Built Into the Silicon Stack
As post-quantum cryptography moves from research into standardization, IoT makers face the challenge of designing hardware that will remain trustworthy over long lifecycles. Pavona addresses this by shipping a complete classical and post-quantum cryptographic stack from day one. Work by ZeroRISC, the Max Planck Institute for Security and Privacy, and Academia Sinica has been folded into the distribution, demonstrating significant performance gains for standardized ML-KEM and ML-DSA algorithms on embedded silicon. The result is not merely support for future algorithms, but tuned implementations that provide 6–9x performance improvements and higher maximum frequencies at near-zero area cost, according to the collaborators’ results. For designers, this means post-quantum cryptography is no longer a bolt-on library but a first-class part of the open source silicon platform, ready to be integrated into roots of trust and cryptographic accelerators without starting from scratch.
Lowering the Barrier for Small Hardware Teams and Makers
Security-critical silicon design has traditionally been dominated by large vendors with proprietary IP and complex certification pipelines. Pavona’s open source approach seeks to change that equation for smaller hardware teams and makers. By offering a curated library of security IP, a composition engine and clear getting-started documentation, the platform reduces the effort required to integrate robust IoT security hardware into custom chips. Hardware-native continuous integration and silicon-proven reference designs help bridge the gap between simulation and tape-out, making it easier to move from prototype to production. For developers building microcontrollers, secure elements or chiplets, the ability to reuse certification-aligned components can shorten design cycles and clarify the path to compliance. Instead of wrestling with fragmented IP and ad-hoc security blocks, teams can assemble a consistent root-of-trust-based architecture that is already aligned with industry standards and ready for scaling across product lines.
Toward a Community-Governed Ecosystem for IoT Security Hardware
Pavona’s governance is as important as its technology for long-term IoT security. Hosted by GlobalPlatform, the project is overseen by a Governing Board that funds operations and an independent Technical Steering Committee that manages the roadmap. This structure is modeled on successful open source projects such as Yocto and Zephyr, emphasizing neutral, community-driven development rather than single-vendor control. Founding members span semiconductor manufacturers, AI companies, IP providers and academic institutions, reflecting a broad interest in an open, certification-aligned hardware security ecosystem. For IoT makers, this means the core building blocks of secure hardware design—roots of trust, cryptographic engines and post-quantum cryptography—are evolving in a transparent, collaborative environment. As open source silicon reaches an inflection point, Pavona positions itself as a central hub where shared, production-grade designs can be reused, improved and certified, accelerating secure-by-default adoption across the connected device landscape.